The present invention relates to a semiconductor memory device, and more particularly to a mode setting circuit and method of a semiconductor memory device for selectively enabling a specific operation mode out of preset operation modes.
To enable a variety of operation modes using the identical device, a fuse select circuit has been conventionally utilized. That is, a fuse corresponding to a desired specific operation mode is disconnected to activate the specific operation mode. However, in such case, once a device is set to one operation mode, it is impossible to be converted to another operation mode due to the physical characteristic of the fuse select circuit.
To overcome such a disadvantage, a configurable mode setting circuit has proposed. A plurality of operation modes are set within the mode setting circuit and signals received from the exterior are combined, thereby selecting the specific operation mode out of the preset operation modes. The mode setting circuit sets the specific operation mode during an enabled interval of a mode setting control signal after combining a control signal synchronized with a row address strobe signal RAS with a row address generated from a row address buffer.
Since the mode setting is implemented under a write enable CAS before RAS (WCBR) condition, it will be readily understood that control signals having information of a column address signal and a write enable signal are needed.
FIGS. 1A and 1B illustrate such conventional mode setting circuits. A mode setting control signal WCBRSET, a row address signal RAi generated from the row address buffer and a constant source voltage signal .phi.VCCH are supplied to the mode setting circuits of FIGS. 1A and 1B, and a mode setting signal MDSTi is generated therefrom. The constant source voltage signal .phi.VCCH is maintained at logic "low" during power-down of a source voltage to set a device to an initial mode. After power-up of the source voltage, the constant source voltage .phi.VCCH is maintained at logic "high".
Referring to FIG. 1A, an inverter 2 receives the mode setting control signal WCBRSET. A PMOS transistor 4 has a source electrode connected to a source voltage VCC, and a gate electrode connected to the output signal of the inverter 2. A PMOS transistor 6 has a gate electrode connected to the row address signal RAi, a source electrode connected to the drain electrode of the PMOS transistor 4, and a drain electrode connected to an output node N1. An NMOS transistor 8 has a gate electrode connected to the row address signal RAi, and a drain electrode connected to the output node N1. An NMOS transistor 10 has a gate electrode connected to the mode setting control signal WCBRSET, a drain electrode connected to the source electrode of the NMOS transistor 8, and a source electrode connected to a ground voltage VSS. An inverter chain consisting of inverters 12 and 14 latches a signal set at the output node N1. An NMOS transistor 20 has a drain electrode connected to the output node N1, a gate electrode connected to the output signal of an inverter 22 receiving the constant source voltage signal .phi.VCCH, and a source electrode connected to the ground voltage VSS. An inverter chain consisting of inverters 16 and 18 shapes the output signal of the inverter 12 and generates the mode setting signal MDSTi.
The mode setting circuit of FIG. 1B is similar to that of FIG. 1A. A PMOS transistor 24 receiving the constant source voltage signal .phi.VCCH is connected between the source voltage VCC and the output node N1.
The mode setting circuits of FIGS. 1A and 1B can set a specific mode during the enabled interval of the mode setting control signal WCBRSET. The specific mode can be set at a desired time by the combination of the row address signal RAi generated from the row address buffer.
In FIG. 1A, if the mode setting control signal WCBRSET is enabled to logic "high", the PMOS and NMOS transistors 4 and 10 are turned on, enabling the mode setting circuit. After power-up, the constant source voltage signal .phi.VCCH of logic "high" is applied to the inverter 22, and the NMOS transistor 20 with the gate electrode connected to the output signal of the inverter 22 is turned off. Therefore, either logic "high" of a source voltage VCC level or logic "low" of a ground voltage VSS level is set at the output node N1 according to the state of the row address signal RAi.
FIG. 2 illustrates a circuit for generating the mode setting control signal WCBRSET shown in FIGS. 1A and 1B. FIG. 3 illustrates an example of operation of FIG. 2.
Referring to FIG. 2, there are supplied control signals .phi.RD and .phi.RAR generated in synchronization with an antiphase of the row address strobe signal RAS, the row address signal RAi generated from the row address buffer, and a meter control signal WCBRB generated by the combination of a column address signal, a row address signal and a write enable signal under the write enable CAS before RAS (WCBR) condition. A NOR gate 28 receives the master control signal WCBRB and the output signal of an inverter 26 receiving the control signal .phi.RD. An inverter 30 receives the row address signal RAi. An inverter chain consisting of inverters 32, 34, 36 and 38 receives the control signal .phi.RAR. A NAND gate 40 receives the output signal of the NOR gate 28 and the output signals of the inverters 30 and 38. An inverter 42 receives the output signal of the NAND gate 40 and generates the mode setting control signal WCBRSET. Resistors R1, R2 and capacitors C1, C2 connected to the inverter chain function as time delay elements.
As indicated in FIG. 3, if the control signal .phi.RD, the master control signal WCBRB, and the control signal .phi.RAR are respectively enabled to logic "high", logic "low" and logic "high", the mode setting control signal WCBRSET of logic "high" is generated after a given time. The mode setting control signal WCBRSET is supplied to the mode setting circuits of FIGS. 1A and 1B.
FIG. 4 illustrates a circuit for generating the master control signal WCBRB shown in FIG. 2. A first logic circuit 44 receives an internal output signal .phi.C of a column address strobe signal buffer, an internal output signal .phi.W of a write enable signal buffer, and an internal output signal .phi.RP of a row address strobe signal buffer. A NOR gate 54 receives control signals .phi.RD1 and .phi.RD2 generated in synchronization with the antiphase of the row address strobe signal RAS. A second logic circuit 46 receives the output signal of the first logic circuit 44 through a node L1. A PMOS transistor 48 has a source electrode connected to the source voltage VCC, a drain electrode connected to the node L1, and a gate electrode connected to the output signal of an inverter 56 receiving the output signal of the NOR gate 54. An inverter chain consisting of inverters 50 and 52 receives the output signal of the second logic circuit 46 and generates the master control signal WCBRB.
In operation, after the master control signal WCBRB is enabled to logic "low" by the signals .phi.C and .phi.W, it is precharged to logic "high" of the source voltage level by the PMOS transistor 48 controlled by the control signals .phi.RD1 and .phi.RD2. It is desirable to rapidly precharge the master control signal WCBRB for the next operation mode. However, it takes much time to precharge the master control signal WCBRB.
In the conventional mode setting circuits, the mode setting control signal WCBRSET is controlled by the control signals .phi.RD and .phi.RAR synchronized with the antiphase of the row address strobe signal RAS. Therefore, in order to set another operation mode after setting a specific operation mode, it is necessary to precharge signals associated with the row address strobe signal RAS, such as the control signals .phi.RD and .phi.RAR. Since it takes at least 30 ns or so to set a specific operation mode, the same time is wasted to convert the operation mode. In a synchronous graphic DRAM (Dynamic Random Access Memory) which operates at a high frequency and frequently varies in the operation mode, the operating speed is thus undesireably lowered, and can result in malfunction.